Leveraging the DSP48E1 block in lightweight cryptographic implementations

Field programmable gate arrays (FPGAs) are generally used in sensor networks for accelerating complex algorithms, either at node or gateway level. The apparition of FPGAs in the market equipped with special blocks for performing logic operations at high-speed and reduced utilization of the platform fabric, allows the implementation of a number of algorithms mainly based on these embedded resources. In this manuscript, we have focused on the Xilinx Artix-7 platform. We have evaluated how replacing logic functions in the implementation of GF(2^m) arithmetics and lightweight block ciphers can reduce the area and, consequently, the cost of the platform. Moreover, we provide an update of an IEEE 802.15.4 accelerator extended with key negotiation capabilities described in previous work. Our results suggest that FPGAs can be employed for developing infrastructure for Wireless Medical Sensor Networks (WMSNs) in cases where encrypting and authenticating a large stream of sensed data is required. In that case, traditional sensor nodes, typically based on microcontrollers and clocked at low frequencies can be ill-suited for real-time applications. Moreover, the fact that large intervals of time are required for executing both encryption and authentication schemes can impact the battery lifetime of the node in comparison of utilizing a separate coprocessor (e.g. based on FPGA) that can be turned on and off when required. Finally, promising results in terms of cost and power consumption are expected when the smallest platforms of the Artix-7 series are available.