Title :
Exploring High-Throughput Computing Paradigm for Global Routing
Author :
Yiding Han ; Ancajas, Dean Michael ; Chakraborty, Koushik ; Roy, Sandip
Author_Institution :
Electr. & Comput. Eng. Dept., Utah State Univ., Logan, UT, USA
Abstract :
With aggressive technology scaling, the complexity of the global routing problem is poised to grow rapidly. Solving such a large computational problem demands a high-throughput hardware platform such as modern graphics processing units (GPUs). In this paper, we explore a hybrid GPU-CPU high-throughput computing environment as a scalable alternative to the traditional CPU-based router. We introduce net-level concurrency (NLC), which is a novel parallel model for router algorithms and aims to exploit concurrency at the level of individual nets. To efficiently uncover NLC, we design a scheduler to create groups of nets that can be routed in parallel. At its core, our scheduler employs a novel algorithm to dynamically analyze data dependencies between multiple nets. We believe such an algorithm can lay the foundation for uncovering data-level parallelism in routing, which is a necessary requirement for employing high-throughput hardware. Detailed simulation results show an average of 4× speedup over NTHU-Route 2.0 with negligible loss in solution quality. To the best of our knowledge, this is the first work on utilizing GPUs for global routing.
Keywords :
graphics processing units; network routing; NLC; NTHU-Route 2.0; data-level parallelism; global routing problem complexity; graphics processing units; high-throughput computing paradigm; high-throughput hardware; high-throughput hardware platform; hybrid GPU-CPU high-throughput computing environment; net-level concurrency; parallel model; router algorithm; scheduler design; technology scaling; traditional CPU-based router; Algorithm design and analysis; Computational modeling; Graphics processing units; Instruction sets; Parallel processing; Routing; Throughput; Global routing; graphics processing unit; high throughput computing;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2012.2234489