FPGA implementation of Hilbert transform via radix-22 pipelined FFT processor

Hilbert transform (HT) is very important algorithm in signal processing. Its application includes constructing analytic signals for various purposes, such as amplitude demodulation, audio production and instantaneous frequency analysis. This paper explains the realization of HT via radix-single-path delay feedback (SDF) pipelined FFT processor. For this purpose, it requires a direct and an inverse FFT implementation. The processor has been developed using hardware description language Verilog on an Xilinx XC5VLX110T FPGA and simulated up to maximum frequency of 273.299 MHz.