Modified MAC unit for low power high speed DSP application using multipler with bypassing technique and optimized adders

Braun multiplier is one of the parallel array multipliers, which is used for unsigned numbers multiplication. This paper aims at an optimization of power and delay of Braun multiplier by using bypassing technique and modification of adders. The dynamic power of a multiplier can be reduced by using bypassing techniques and delay can be reduced by replacing ripple carry adder in the last stage of full adders by optimized adders in different logics, Double pass transistor logic (DPL) and Transmission Gate (TG). Different logic style adders are designed and implemented in 0.13μm CMOS technology and its functional parameters are compared and the best result is incorporated in the column bypassed Braun multiplier. The new multiplier is used to implement a MAC unit which is more efficient.