Tutorial: Introduction to Interconnection Networks from System Area Network to Network on Chips

Author

Amano, Hideharu

Author_Institution

Dept. of Inf. & Comput. Sci., Keio Univ., Yokohama, Japan

fYear

2013

fDate

4-6 Dec. 2013

Firstpage

15

Lastpage

16

Abstract

Interconnection networks connect cab nets in the floors, boards in a cab net, chips on a board, and moudles inside the chip. Since protcols and network structures are not fixed unlike LAN or WAN, there are wide viriety on topologies, routing, flow control and media. As an introduction of two other tutorial sessions ("Future Low-latency Networks for High Performance Computing" and "Research Challenges on 2-D and 3-D Network-on-Chips"), typical interconnection networks and techniques around them are explained with recent examples.

Keywords

local area networks; multiprocessor interconnection networks; network-on-chip; 2D network-on-chips; 3D network-on-chips; cab nets; high performance computing; interconnection networks; low-latency networks; network structures; protocols; system area network; Multiprocessor interconnection; Optical switches; Protocols; Routing; Topology; Tutorials; Wide area networks; Interconnection Networks;

fLanguage

English

Publisher

ieee

Conference_Titel

Computing and Networking (CANDAR), 2013 First International Symposium on

Conference_Location

Matsuyama

Print_ISBN

978-1-4799-2795-1

Type

conf

DOI

10.1109/CANDAR.2013.9

Filename

6726871