Energy-efficient truncated multipliers with scaling

Approximate computing is an attractive approach to energy saving area as many error-tolerant applications can make use of it for preserving energy on battery-powered mobile devices. This paper explores three designs of truncated 8-bit combinational multipliers that provide an approximate result while reducing energy consumption. Truncation methods are presented and analyzed in terms of energy reduction and error distribution. The three designs offer different balances and tradeoffs between accuracy and energy savings, with one of the designs reaching 86% in energy savings at the expense of reduced yet acceptable image quality in an image processing test. All designs resulted in an acceptable PSNR and an excellent performance when tested with SUSAN applications, while performance varied when tested with JPEG applications.