A 5-bit 1.5 GS/s ADC using reduced comparator architecture

Author

Saloni ; Goswami, Mausumi ; Singh, B. Raja

Author_Institution

Dept. of Microelectron., Indian Inst. of Inf. Technol., Allahabad, India

fYear

2013

fDate

16-18 Dec. 2013

Firstpage

1

Lastpage

3

Abstract

Recent trends in mixed-signal design for wireless application require high speed, power-efficient ADCs. Flash ADC architecture is an optimum choice for speed but dissipates power exponentially with increase in resolution. The present work on 5-bit 1.5 GS/s ADC explores new architectural strategy of circuit design in optimizing the power using reduced comparator architecture. The proposed circuit using only 5 comparators when operated with 2.5 V supply, dissipates less (83mW) power and silicon area as compared to existing architectures. The proposed ADC offers an ENOB of 4.60 bits, SNR of 27.2dB, SFDR of 36.21dB, INL and DNL of 0.32L5B and 0.43L5B respectively when simulated using 500nm CMOS MOSIS (AMIS) C5X design kit.

Keywords

CMOS integrated circuits; analogue-digital conversion; comparators (circuits); integrated circuit design; mixed analogue-digital integrated circuits; silicon; CMOS MOSIS C5X design kit; analog-to-digital converters; comparator architecture; flash ADC architecture; integrated circuit design; mixed-signal design; power 83 mW; size 500 mm; voltage 2.5 V; word length 5 bit; Decision support systems; Analog to Digital Converter; High Speed Comparator; Low Power; Multiplexer; Resolution;

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Test Symposium (IDT), 2013 8th International

Conference_Location

Marrakesh

Type

conf

DOI

10.1109/IDT.2013.6727113

Filename

6727113