Title :
FPGA implementation of the m-ary modular exponentiation
Author :
Nadjia, Anane ; Mohamed, Amr
Author_Institution :
CDTA (Centre de Dev. des Technol. Av.), Algiers, Algeria
Abstract :
Modular exponentiation is a key operation of RSA cryptosystem and is very time consuming for large operands. It is performed using successive modular multiplications. This paper describes hardware architecture of the m-ary modular exponentiation with reduced number of Montgomery modular multiplications. This architecture has been implemented on FPGA circuit of Virtex-2 and presents best performances in terms of computation time and occupied resources.
Keywords :
computational complexity; field programmable gate arrays; public key cryptography; FPGA circuit; Montgomery modular multiplications; RSA cryptosystem; Virtex-2; computation time; hardware architecture; m-ary modular exponentiation; Complexity theory; Cryptography; Field programmable gate arrays; Hardware; Memory management; Multiplexing; FPGA; Montgomery modular exponentiation; RSA;
Conference_Titel :
Design and Test Symposium (IDT), 2013 8th International
Conference_Location :
Marrakesh
DOI :
10.1109/IDT.2013.6727140
