• DocumentCode
    678794
  • Title

    FPGA implementation of the m-ary modular exponentiation

  • Author

    Nadjia, Anane ; Mohamed, Amr

  • Author_Institution
    CDTA (Centre de Dev. des Technol. Av.), Algiers, Algeria
  • fYear
    2013
  • fDate
    16-18 Dec. 2013
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    Modular exponentiation is a key operation of RSA cryptosystem and is very time consuming for large operands. It is performed using successive modular multiplications. This paper describes hardware architecture of the m-ary modular exponentiation with reduced number of Montgomery modular multiplications. This architecture has been implemented on FPGA circuit of Virtex-2 and presents best performances in terms of computation time and occupied resources.
  • Keywords
    computational complexity; field programmable gate arrays; public key cryptography; FPGA circuit; Montgomery modular multiplications; RSA cryptosystem; Virtex-2; computation time; hardware architecture; m-ary modular exponentiation; Complexity theory; Cryptography; Field programmable gate arrays; Hardware; Memory management; Multiplexing; FPGA; Montgomery modular exponentiation; RSA;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design and Test Symposium (IDT), 2013 8th International
  • Conference_Location
    Marrakesh
  • Type

    conf

  • DOI
    10.1109/IDT.2013.6727140
  • Filename
    6727140
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=678794