A 4.2GS/s 4-bit ADC in 45nm CMOS technology

Author

Kumar, Manoj ; Varshney, S.

Author_Institution

Dept. of Microelectron., Indian Inst. of Inf. Technol., Allahabad, India

fYear

2013

fDate

19-21 Dec. 2013

Firstpage

24

Lastpage

28

Abstract

In this paper an analog to digital converter architecture is introduced. The proposed design is based on a mixed approach of flash type ADC and SAR type ADC. This design offers lesser number of comparators and so low power consumption with much less circuit complexity in comparison to conventional flash ADC architecture. Based on the proposed idea, a 4-bit ADC is simulated in Cadence virtuoso Tool using 45nm CMOS technology with power supply voltage of ± 0.6 V. Maximum sampling speed of ADC is achieved as 4.2 GS/s. The ADC consumes 72μW of power. The measured INL and DNL are 0.40 LSB and 0.42 LSB respectively.

Keywords

CMOS integrated circuits; analogue-digital conversion; low-power electronics; CMOS technology; SAR type ADC; analog-digital converter; circuit complexity; flash type ADC; low power consumption ADC; size 45 nm; successive approximation register; voltage 0.6 V; Asia; CMOS integrated circuits; Conferences; Inverters; Logic gates; Microelectronics; Power supplies; Analog-digital conversion (ADC); DNL; Flash ADCs; INL;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics and Electronics (PrimeAsia), 2013 IEEE Asia Pacific Conference on Postgraduate Research in

Conference_Location

Visakhapatnam

Print_ISBN

978-1-4799-2750-0

Type

conf

DOI

10.1109/PrimeAsia.2013.6731172

Filename

6731172