DocumentCode
679729
Title
Frequency compensation in two-stage operational amplifiers for achieving high 3-dB bandwidth
Author
Malhotra, Sanjay ; Mishra, Anadi ; Rakesh, B.R. ; Gupta, Arpan
Author_Institution
Electr. & Electron., BITS Pilani, Pilani, India
fYear
2013
fDate
19-21 Dec. 2013
Firstpage
107
Lastpage
110
Abstract
A frequency compensation technique for achieving high 3-dB bandwidth in two-stage operational amplifiers is demonstrated in this paper. Due to the phenomenon of pole splitting in Miller´s Compensation technique in classical op-amp, the 3-dB bandwidth reduces drastically. The technique demonstrated in this paper is a modification of Miller´s Compensation technique to achieve a significant improvement in the 3-dB bandwidth by introducing an extra stage, consisting of MOS transistors (MOST). The coupling capacitor and a PMOS transistor operating in triode region is connected between the output of the extra stage and the input of the second stage. The simulations were carried out in Cadence VIRTUOSO environment using 0.18 μm CMOS process technology.
Keywords
CMOS integrated circuits; compensation; operational amplifiers; CMOS process technology; Cadence VIRTUOSO environment; MOS transistors; MOST; Miller compensation technique; PMOS transistor; classical op-amp; coupling capacitor; frequency compensation technique; pole splitting; size 0.18 mum; triode region; two stage operational amplifiers; Bandwidth; CMOS integrated circuits; Capacitors; Couplings; Gain; MOSFET; Operational amplifiers; 3-dB Bandwidth; Coupling Capacitor; Frequency Compensation; Phase Margin; Two-Stage Operational Amplifier;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronics and Electronics (PrimeAsia), 2013 IEEE Asia Pacific Conference on Postgraduate Research in
Conference_Location
Visakhapatnam
Print_ISBN
978-1-4799-2750-0
Type
conf
DOI
10.1109/PrimeAsia.2013.6731187
Filename
6731187
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