A novel concurrent BIST architecture for register based recording and windowed playback

In this paper we present a novel concurrent BIST scheme termed as “Register based Recording and Windowed Playback”. We propose a method to test digital ICs during normal operation. The hardware used for online-offline testing observes the normal inputs and eliminates those from the test set. Unlike the previous method (SWiM), a register is used to record the normal inputs in the online mode and in the offline mode the vectors not hit in the normal mode are checked window by window and are applied to the Circuit Under test (CUT). The windowed approach for playback reduces the hardware while the non-windowed approach for recording reduces the Concurrent Test Latency (CTL). The architecture is implemented on Verilog-HDL, has been simulated using nc-sim and the synthesis has been done using RTL-compiler with TSMC 180nm technology. The Concurrent test Latency has reduced by 97.9% for 8-bit input circuit and 99.9% for 16-bit input circuit.