Improving FPGA placement with a self-organizing map

Author

Bostelmann, Timm ; Sawitzki, Sergei

Author_Institution

FH Wedel (Univ. of Appl. Sci.), Wedel, Germany

fYear

2013

fDate

9-11 Dec. 2013

Firstpage

1

Lastpage

6

Abstract

This work shows how the results of netlist placement for island style FPGAs can be improved by the use of a self-organizing map. The structural information of a netlist is used to generate training vectors, which are classified by a self-organizing map. This classification is used to generate an initial placement for the renown iterative simulated annealing algorithm. By applying this procedure both the length of the critical path and the needed routing resources are reduced in comparison to the classical random initialization.

Keywords

electronic engineering computing; field programmable gate arrays; island structure; iterative methods; learning (artificial intelligence); self-organising feature maps; simulated annealing; critical path length; island-style FPGA placement improvement; iterative simulated annealing algorithm; netlist placement; routing resources; self-organizing map; structural information; training vector generation; Benchmark testing; Computer architecture; Field programmable gate arrays; Microprocessors; Neurons; Training; Vectors;

fLanguage

English

Publisher

ieee

Conference_Titel

Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on

Conference_Location

Cancun

Print_ISBN

978-1-4799-2078-5

Type

conf

DOI

10.1109/ReConFig.2013.6732302

Filename

6732302