Processor arrays generation for matrix algorithms used in embedded platforms

Matrix algorithms are an important part of many digital signal processing applications as they are core kernels that usually need to be applied many times. Hardware assisted implementations using FPGAs provide a good compromise between performance, cost and power consumption. This paper presents a high level synthesis approach to generate embedded processor arrays for matrix algorithms based on the polytope model. The proposed approach provides a solution for efficient data memory accesses and data transferring for feeding the processor array, as well as it provides support for solving a set of problem size depending on FPGA available resources. The proposed approach has been validated by generating processor arrays for two case studies targeted for a Spartan-6 device. Results show that the implemented array outperforms hardware and software implementations targeted to embedded platforms as well.