RALP: Reconvergence-aware layer partitioning for 3D FPGAs

In 3D FPGA designs, the circuit elements are distributed among multiple layers. Therefore, the partition strategies will influence the optimization of the entire design. Without the layout information, it is quite difficult to evaluate the effect of partitioning before placement. As a prior estimation model, re-convergence has shown its efficiency to estimate wire length before placement in 2D FPGA designs. However, when it comes to 3D FPGA, the traditional method is no longer applicable due to the change of routing architecture. In this paper, we propose a novel prior estimator called 3D-reconvergence to evaluate wire length of the netlists in 3D FPGA designs. A reconvergence-aware layer partition (RALP) algorithm for 3D FPGA design is proposed. Experimental results show that our partitioning approach could lead to better physical layout results. Compared with the traditional min-cut based partitioning approach, the design flow with RALP can obtain better routing results by reducing 7.06% wire length and 4.86% delay for 2-layer designs, 4.71% wire length and 4.73% delay for 3-layer designs.