• DocumentCode
    680090
  • Title

    SoC self-integration mechanism for dynamic reconfigurable systems based on collaborative macro-function units

  • Author

    Dumitriu, Victor ; Kirischian, Lev

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Ryerson Univ., Toronto, ON, Canada
  • fYear
    2013
  • fDate
    9-11 Dec. 2013
  • Firstpage
    1
  • Lastpage
    7
  • Abstract
    For most multi-modal stream processing tasks Dynamic Reconfigurable Systems-on-Chip (SoC) have demonstrated high efficiency in cost and power. These systems utilize partial reconfiguration for dynamic adaptation to changes in the workload or in environment. Mostly, reconfiguration mechanisms are based on central resource management sub-systems deployed in a CPU-core. In this paper we propose a novel mechanism for SoC self-integration based on Collaborative Macro-Function Units (CMFU). Each CMFU consist of a function-specific IP-core combined with a Co-op unit. Co-op units allow CMFUs to co-operate with each other and provide run-time self-integration into the SoC. As well, they provide self-initiation, self-termination and self-synchronization procedures without any central control. This allows a dramatic increase in SoC flexibility, reliability and, finally, survivability. It is specifically important to mitigate hardware faults caused by radiation effects or aging of the die. The proposed mechanism was implemented and tested on a Xilinx Kintex-7 FPGA platform. It was shown that CMFUs can perform self-integration and relocation inside the FPGA almost seamlessly. The hardware overhead of the Co-op unit was relatively small (less than 10% of the entire CMFUs).
  • Keywords
    fault tolerant computing; field programmable gate arrays; integrated circuit reliability; system-on-chip; CMFU; CPU-core; Co-op unit; SoC flexibility; SoC reliability; Xilinx Kintex-7 FPGA platform; central resource management subsystems; collaborative macrofunction units; dynamic reconfigurable systems; function-specific IP-core; hardware faults mitigation; hardware overhead; multimodal stream processing; partial reconfiguration utilization; run-time self-integration; self-initiation procedures; self-synchronization procedures; self-termination procedures; systems-on-chip; Collaboration; Connectors; Field programmable gate arrays; Hardware; IP networks; Resource management; System-on-chip; Collaborative components; Dynamic partial reconfiguration; FPGA; Reconfigurable systems; Reconfiguration techniques; Self-integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on
  • Conference_Location
    Cancun
  • Print_ISBN
    978-1-4799-2078-5
  • Type

    conf

  • DOI
    10.1109/ReConFig.2013.6732331
  • Filename
    6732331