A 1024 bit RSA coprocessor in CMOS

This paper presents the architecture and model of a modular exponentiation hardware for RSA public key cryptography algorithm. A radix-2 Montgomery modular multiplication hardware based on a systolic implementation was designed. A kogge-stone adder was designed to reduce the critical path and improve throughput. The data path and dataflow of the Montgomery modular multiplier and the exponentiation hardware is fully exploited. Cadence© Encounter RTL Compiler was used to synthesize the RTL code described in Verilog HDL. The coprocessor was implemented with standard cells library from 0.18μm CMOS IBM 7RF technology. This implementation runs 1024 bit RSA encryption and decryption process in 8.44ms and the throughput of this implementation is 121.269Kbps.