Chopped Logarithmic Programmable Gain Amplifier intended to EEG acquisition interface

This paper concerns the design and implementation of a new fully integrated Chopped Logarithmic Programmable Gain Amplifier (CLPGA) intended for a front-end EEG acquisition interface. The proposed front-end has low-input referred noise and high-common mode rejection ratio (CMRR) compared to Instrumentation Amplifier features, and its rail-to-rail topology allows electrode offset rejection. The logarithmic amplification block is composed of three cascaded true logarithmic amplification stages. Also, a chopper stabilization technique is used to improve the noise figure. This front-end interface is followed by an analog to digital convertor, and in order to prevent EEG signal distortion, the magnitude of the later signal is controlled by implementing new programming gain approach. Post-layout simulation in 0.18 μm CMOS technology demonstrates a High CMRR of 284 dB @50/60 Hz, an input referred noise of ~0.5 mVrs on 100 Hz BW and an input common mode ranges from 0.6 to 1.12 V for 1.8 V supply. The measured power consumption is 1.2 mW and the effective CLPGA area is 0.5 mm2 including the digital part needed for programming the gain.