DocumentCode
6810
Title
SPREAD: A Streaming-Based Partially Reconfigurable Architecture and Programming Model
Author
Ying Wang ; Xuegong Zhou ; Lingli Wang ; Jian Yan ; Luk, Wayne ; Chenglian Peng ; Jiarong Tong
Author_Institution
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
Volume
21
Issue
12
fYear
2013
fDate
Dec. 2013
Firstpage
2179
Lastpage
2192
Abstract
Partially reconfigurable systems are promising computing platforms for streaming applications, which demand both hardware efficiency and reconfigurable flexibility. To realize the full potential of these systems, a streaming-based partially reconfigurable architecture and unified software/hardware multithreaded programming model (SPREAD) is presented in this paper. SPREAD is a reconfigurable architecture with a unified software/hardware thread interface and high throughput point-to-point streaming structure. It supports dynamic computing resource allocation, runtime software/hardware switching, and streaming-based multithreaded management at the operating system level. SPREAD is designed to provide programmers of streaming applications with a unified view of threads, allowing them to exploit thread, data, and pipeline parallelism; it enhances hardware efficiency while simplifying the development of streaming applications for partially reconfigurable systems. Experimental results targeting cryptography applications demonstrate the feasibility and superior performance of SPREAD. Moreover, the parallelized Advanced Encryption Standard (AES), Data Encryption Standard (DES), and Triple DES (3DES) hardware threads on field-programmable gate arrays show 1.61-4.59 times higher power efficiency than their implementations on state-of-the-art graphics processing units.
Keywords
Auger electron spectra; cryptography; graphics processing units; multi-threading; reconfigurable architectures; resource allocation; 3DES hardware threads; AES; SPREAD; cryptography applications; data encryption standard; dynamic computing resource allocation; field programmable gate arrays; graphics processing units; hardware efficiency; operating system level; parallelized advanced encryption standard; point to point streaming structure; reconfigurable flexibility; software/hardware multithreaded programming model; software/hardware switching; software/hardware thread interface; streaming applications; streaming based multithreaded management; streaming based partially reconfigurable architecture; triple DES; Hardware; Instruction sets; Operating systems; Parallel processing; Runtime; Switches; Hardware thread; parallelism; partial reconfiguration; streaming application;
fLanguage
English
Journal_Title
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher
ieee
ISSN
1063-8210
Type
jour
DOI
10.1109/TVLSI.2012.2231101
Filename
6409493
Link To Document