Sampling Clock Synchronization with PID controller for optical OFDM systems

Sampling Clock Synchronization is one of the most important procedures in Optical Orthogonal Frequency Division Multiplexing (OOFDM) systems as OFDM systems are extremely sensitive and vulnerable to clock synchronization errors. Moreover, in such high speed communication systems, it is unsuitable in practice that highly complex digital signal processing (DSP) technology is utilized in sampling clock synchronization, which will not only cause the high hardware resource consumption in Field Programmable Gate Array (FPGA), but also increase the whole system complexity. In this paper, we proposed a sampling clock synchronization scheme based on Proportional Integral Derivative (PID) automation algorithm. The proposed scheme extracts the sampling clock offset (SCO) from received symbols and then utilizes PID controller to adjust the sampling clock implemented via Voltage Controlled Oscillator (VCO). Inherited the characteristic from PID controller, the low complexity is also one of the remarkable advantages of the proposed scheme. Additionally, the proposed sampling clock synchronization scheme operates well in automatic precise sampling clock synchronization and has fast frequency tracking characteristic. Experimental results verified that the proposed scheme can effectively compensate the SCO and improve the system performance.