Pipelining Harris corner detection with a tiny FPGA for a mobile robot

With their parallelizable inner structures, field programmable gate array (FPGA) are increasing their popularity in today´s embedded systems. In this paper, we present an implemented, unique and pipelined FPGA architecture designed with Verilog HDL to be used on a mobile robot for detecting corners in colored stereo images using Harris corner detection (HCD) algorithm in real time. The architecture consists of 3 pipelined modules and processes RGB555 formatted images in 640×480 resolution. The design is implemented on Xilinx´s ML501 board having a XC5VLX50 FPGA, one of the smallest FPGAs of Virtex-5 series. Raw and processed data are stored into a single DDR2 memory of Micron, MT4HTF3264HY on the board, allowing only a single read or write operation at a time. By using less than 75% of FPGA resources and a 100MHz system clock, we achieved a corner detection rate of 0.33 pixels per clock cycle (ppcc) corresponding to a corner detection frequency of 54Hz for the stereo images.