Reducing worst-case execution time of hybrid SPM-caches

This paper studies the Scratch-Pad Memory (SPM) allocation for a hybrid SPM and cache architecture, where an SPM and a cache memory are placed on-chip in parallel to cooperatively improve performance and/or energy efficiency. To benefit hard real-time systems, this paper proposes and evaluates four SPM allocation strategies to reduce the worst-case execution time (WCET) for hybrid SPM-caches with different complexities. These algorithms differ by whether or not they can cooperate with the cache or be aware of the WCET. Our evaluation shows that the cache-aware and WCET-oriented SPM allocation can maximally reduce the WCET with minimum or even positive impact on the average-case execution time (ACET).