Multiply-accumulator using modified booth encoders designed for application in 16-bit RISC processor

In this paper, multiply-accumulator (MAC) is designed for application in simple 16-bit RISC processors to enhance the processor´s capability by adding new instruction set. Creation of new instruction set is achieved by modifying the processor´s architecture using Verilog Hardware Description Language (Verilog HDL). The new instruction set has simple structure, and can be fully compatible with the existing architecture. The MAC involves 16×16 bit multiplier using modified Booth encoders and the accumulation result is stored in two 16-bit register-pair. The multiplier consists of Booth algorithm, Wallace tree and carry look-ahead adder (CLA). The RISC processor in this paper is a 16-bit pipelined RISC processor using Harvard architecture and the pipeline consists of the instruction fetch unit, decode unit, the front-end logic execution unit, arithmetic execution unit and register access unit. The simulation result shows that correct output has been observed, and the MAC architecture has been verified and synthesized on FPGA platform successfully.