Efficient VLSI architecture of JPEG2000 encoder

In this paper, an efficient VLSI architecture of JPEG2000 encoder is given. The proposed architecture functionally consists of three main parts: discrete wavelet transform (DWT), block encoder (i.e., known as embedded block coding with optimized truncation (EBCOT), which is combined with bitplane coder, MQ coder and rate-distortion (RD) truncation) and memory management unit (MMU). For DWT, high-performance line-based lifting implementation supporting both 5/3 reversible and 9/7 irreversible filters is used to gain higher computational accuracy under lower hardware overhead constraints. For the block encoder, the bitplane parallel EBCOT architecture and efficient MQ coder scheme are adopted to increase parallelism and hardware utility. The hardware-oriented RD truncation is proposed to reduce processing time. MMU is employed to switch on-chip and off-chip memories in terms of image size for the consideration of power consumption. Experimental results demonstrate that the proposed efficient architecture attains a throughput of 120M Samples per second.