DocumentCode :
683176
Title :
Process optimization for Potential Induced Degradation improvement on cell level
Author :
Ta-Ming Kuan ; Chih-Chiang Huang ; Li-Guo Wu ; Yu-Chih Chan ; Cheng-Yeh Yu
Author_Institution :
TSEC Corp., Hsinchu, Taiwan
fYear :
2013
fDate :
16-21 June 2013
Firstpage :
2224
Lastpage :
2226
Abstract :
The Potential Induced Degradation (PID) has been known one of the important quality indexes of photovoltaic cells and modules in last few years. There have been several PID stability test methods and researches to explain the root cause of PID to achieve one common goal, a robust PV cell/module/system for longer lifetime. In this study, we have demonstrated process optimization techniques to improve cell-level PID performance. The Anti-Reflection Coating (ARC) layer has been optimized for better film quality. Further optimization of dual ARC layer design is applied to improve PID resistant capability. By using above techniques, within 5% degradation and no EL darkened area after PID test was obtained. Furthermore, it is known that PID performance and cell efficiency are trade-off, better PID performance will cause efficiency degradation. In this study, we successfully demonstrated cell efficiency gain by 0.3%abs with our PID-free process. Detailed process and PID measurement results will be discussed based on optimized process techniques.
Keywords :
antireflection coatings; photovoltaic cells; solar cells; PID stability test methods; anti-reflection coating; cell-level PID performance; photovoltaic cells; potential induced degradation; process optimization; quality indexes; resistant capability; Degradation; Etching; Optimization; Photovoltaic cells; Resistance; Silicon; Standards; PID; potential induced degradation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Photovoltaic Specialists Conference (PVSC), 2013 IEEE 39th
Conference_Location :
Tampa, FL
Type :
conf
DOI :
10.1109/PVSC.2013.6744918
Filename :
6744918
Link To Document :
بازگشت