DocumentCode
683227
Title
Growth of vertical silicon nanowires array using electrochemical alternative
Author
Van Hoang Nguyen ; Watanabe, Hiromi ; Hoshi, Yusuke ; Kiguchi, Takanori ; Konno, Takaaki ; Samukawa, Seiji ; Usami, Noritaka
Author_Institution
Grad. Sch. of Eng., Nagoya Univ., Nagoya, Japan
fYear
2013
fDate
16-21 June 2013
Firstpage
2443
Lastpage
2446
Abstract
Silicon nanowires have been grown on Si (111) substrate using the vapor-liquid-solid (VLS) via anodic aluminum oxide (AAO) fabrication and gold plating deposition. The pore diameters of AAO are expected to be closely related with the size of gold catalyst as well as the diameter of the subsequently grown silicon nanowires. The nanochannel diameter of AAO template was controlled by modifying the applied potential in different values. Filling the small amount of Au at the bottom of AAO template was realized by electrochemically plating technique. The sub-20 nm diameter gold nanowires were formed thanks to long plating duration. The growth of vertical silicon nanowires by VLS techniques was carried out in different growth time using disilane as a source gas.
Keywords
electroplating; elemental semiconductors; gold; nanofabrication; nanowires; semiconductor growth; silicon; Si; Si (111) substrate; Si-Au; anodic aluminum oxide fabrication; disilane; electrochemically plating technique; gold plating deposition; nanochannel; pore diameters; size 20 nm; vapor-liquid-solid method; vertical nanowire array; Arrays; Etching; Films; Gold; Nanowires; Silicon; Substrates; Anodic Aluminum Oxide; gold plating; silicon nanowires; vapor liquid solid;
fLanguage
English
Publisher
ieee
Conference_Titel
Photovoltaic Specialists Conference (PVSC), 2013 IEEE 39th
Conference_Location
Tampa, FL
Type
conf
DOI
10.1109/PVSC.2013.6744969
Filename
6744969
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