Die attach delamination resolution for exposed pad LQFP with large package size

Integrated circuit (IC) package delamination defect refers to interface adhesion failures between either die to die attach material, die attach material to die paddle interface, or mold compound material to die paddle interface delamination, all of which are equally critical, in particular, for exposed pad Low Profile Quad Flat Packages (LQFPs) for large package sizes. Most of the devices with minor delamination are not easily detectable during device testing, but may potentially cause functional failure in certain applications in the field, especially after external mechanical stresses have been applied. There is no option of reworking these devices, and the IC manufacturer may suffer heavy cost impacts if the suspected defective units have to be recalled as customer return. Thus, the semiconductor industry is aggressively striving to improve the delamination performance in IC packaging. However, to date, this task is complicated and difficult as the defective failure is highly dependent on the compatibility of the material characteristic that may influence the entire IC package system under certain stress level, both mechanical and thermal stresses. In the first part of this paper, a detailed process mapping is established to determine the possible delamination root causes by performing a fish bone diagram mapping on the cause and effect. The different suspected causes include, among others, contribution from contamination factors on the die back and lead frame surfaces. In addition, a preliminary check on the existing cure profile and recommended profile from die attach material supplier was studied to enhance the adhesion between die back to die attach material interfaces. A process characterization is done to optimize the die attach cure profile recipe to enable zero voids formation, and at the same time, achieve good die pull strength value. In the second portion of this paper, a detailed die stress modeling was performed to examine various suspected high str- ss point in the IC package for better understanding in terms of overall package mechanical behavior. The critical factors such as the die edge to flag edge clearance, different bond line thickness (BLT), different die thickness and different fillet height phenomenon were analyzed. Finally, a detailed design of experiment (DOE) was generated based on the combination of the significant factors from the die stress modeling and also, from the material characteristic result analysis. The robustness of the package interface was then tested based on the reliability performance up to the required number of temperature cycling tests. The proper selection of leadframe die paddle size, epoxy material and epoxy cure profile was found to be able to successfully passed temperature cycling at -50°C to 150°C up to 2000 cycles.