Title :
Low power multilevel current-mode interconnect system with RLC Model
Author :
Xinsheng Wang ; Liang Han ; Mingyan Yu
Author_Institution :
Sch. of Astronaut., Harbin Inst. of Technol., Harbin, China
Abstract :
In this paper, we introduce a novel multi-level current mode for RLC interconnection system, which can effectively reduce the delay on the interconnect line and consume low power over long interconnect line. Interconnect wire inductance can decrease interconnect power and affect interconnect system frequency, while the technology of inductive peaking, which counteracts the high frequency attenuation due to the capacitance, will still work well. Simulation results show that the power consumption of the RLC interconnect system is 172uW, which is improved 100 times more than voltage mode buffer insertion techniques and lower than other current mode interconnect systems. Moreover interconnect wire power is also reducing over 6.6% due to interconnect inductance effect in 1mm interconnect wire.
Keywords :
RLC circuits; VLSI; integrated circuit interconnections; RLC interconnect system; RLC interconnection system; RLC model; VLSI; current mode interconnect system; delay reduction; frequency attenuation; inductive peaking technology; interconnect inductance effect; interconnect line; interconnect system frequency; interconnect wire inductance; interconnect wire power; low-power multilevel current-mode interconnect system; power 172 muW; size 1 mm; voltage mode buffer insertion technique; Interconnect Inductance; Multilevel signaling; current mode; integrated circuit; low power;
Conference_Titel :
Information Science and Control Engineering 2012 (ICISCE 2012), IET International Conference on
Conference_Location :
Shenzhen
Electronic_ISBN :
978-1-84919-641-3
DOI :
10.1049/cp.2012.2310