A novel voltage limiter circuit for passive RFID tag

This paper presents a novel voltage limiter circuit used in passive RFID tag to avoid possible damage to the tag. The proposed voltage limiter design takes advantage of the implemented band-gap reference to provide low temperature and process deviation of the limiting voltage and has low current consumption. The simulation result shows the limiting voltage is 2V with a voltage variation of 81.86mV. The quiescent current is only 120nA. The circuit is designed with TSMC 0.18μm CMOS process. The circuit area is 92×96μm².