Design of PCI-104 bus interface of lowpower embedded CPU based on FPGA

In the application of some embedded systems such as the ship-borne routers, ATM machines and so on, many low-power embedded CPU needs connection with PCI-104 bus. However, these low-power embedded CPUs don´t have the bus interface of PCI-104 (PCI). In order to solve this problem, this paper designs FPGA-based PCI-104 bus interfaces of the low-power embedded CPU. Through the analysis of PCI-104 bus protocol and the corresponding interface signal sequence, the method of Top_Down is applied to the modeling of the seven functional modules of PCI-104 bus interface such as the configuration register module, base address check module, state machine module, etc. Besides, in consideration that these CPUs can also be taken as the coprocessors, the master and target device interfaces of PCI-104 bus are programmed with the utilization of Verilog language, and the finite-state machine of the master device and the target device is structured in detail. Through the Modelsim simulation verification, it has been proved that the interface can meet the timing requirements of the PCI-104 bus specification, so as to connect these low-power embedded CPUs with PCI-104 bus expansion board. It also can realize to upgrade CPU on the PCI-104 bus board.