• DocumentCode
    685527
  • Title

    Harnessing SMT-Based Bounded Model Checking through Stateless Explicit-State Exploration

  • Author

    Weiqiang Kong ; Leyuan Liu ; Ando, Takehiro ; Yatsu, Hirokazu ; Hisazumi, Kenji ; Fukuda, Akira

  • Author_Institution
    Grad. Sch. of IS&EE, Kyushu Univ., Fukuoka, Japan
  • Volume
    1
  • fYear
    2013
  • fDate
    2-5 Dec. 2013
  • Firstpage
    355
  • Lastpage
    362
  • Abstract
    We propose a hybrid approach to improving the verification performance of SMT-based bounded model checking for LTL properties. In this approach, stateless explicit-state exploration is utilized to traverse, under the constraints of bounded context switches, the state space of a system design and memorize legal execution paths. These paths are classified according to certain predicates into path clusters, which are then encoded into propositional formulas representing, together with the encoded formula for an LTL property, independent BMC instances. Such BMC instances are solved with SMT solvers running on mutilcores in parallel. Once a counterexample is found for one of the instances, the entire model checking terminates. This hybrid checking procedure progresses in an incremental fashion until either a counterexample is found or the user-specified bound is reached. We have implemented this proposed hybrid approach in a tool called Garakabu2 with CVC4 as its backend solver. The experimental results show that Garakabu2 often outperforms the state-of-the-art pure BMC methods implemented in SAL infinite bounded model checker for both safety and liveness properties.
  • Keywords
    computability; formal verification; parallel processing; temporal logic; BMC instances; CVC4; Garakabu2; LTL properties; SAL infinite bounded model checker; SMT solvers; SMT-based bounded model checking; backend solver; bounded context switches; hybrid checking procedure; legal execution paths; linear temporal logic; multicores; path clusters; propositional formulas; satisfiability modulo theory; stateless explicit-state exploration; system design state space; verification performance; Context; Encoding; Model checking; Safety; Silicon; Switches; System recovery; Bounded Model Checking; Linear Temporal Logic; Stateless Explicit-State Exploration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Software Engineering Conference (APSEC), 2013 20th Asia-Pacific
  • Conference_Location
    Bangkok
  • ISSN
    1530-1362
  • Print_ISBN
    978-1-4799-2143-0
  • Type

    conf

  • DOI
    10.1109/APSEC.2013.55
  • Filename
    6805426