Title :
64 bit green ALU design using clock gating technique on ultra scale FPGA
Author :
Kumar, Tanesh ; Pandey, Bishwajeet ; Das, Teerath ; Islam, Shekh Md Mahmudul
Author_Institution :
Dept. of Comput. Sci., South Asian Univ., New Delhi, India
Abstract :
In this paper 64-bit energy efficient Arithmetic Logic Unit (ALU) is designed in verilog with the help of clock gating technique. We can reduce dynamic power and dynamic current of 64-bit ALU by using clock gating technique. This design is implemented on XC6VLX75T device, -3 speed grade and Virtex-6 FPGA. When clock logic is applied to target device, we are achieving 67.74% and 65.84% less reduction in clock power and 93.82% and 93.71% less reduction in Leakage power, when the device is operating on frequencies 1GHz and 10GHz respectively. On 1GHz, there is 66.93% less reduction in overall dynamic power of 64-bit ALU, when clock gate is added to the device. Dynamic current is reduced to 39.53% at operating frequency of 1THz, when clock gating is used.
Keywords :
clocks; digital arithmetic; field programmable gate arrays; hardware description languages; logic design; power aware computing; Verilog; Virtex-6 FPGA; XC6VLX75T device; clock gate; clock gating technique; clock logic; dynamic power reduction; energy efficient arithmetic logic unit; frequency 1 GHz to 10 GHz; frequency 1 THz; green ALU design; leakage power reduction; ultra scale FPGA; word length 64 bit; Clocks; Energy efficiency; Field programmable gate arrays; Logic gates; Power demand; Registers; Arithmetic Logic Unit (ALU); Clock Gating; Clock Power; Dynamic Power; Energy Efficient Design; FPGA; I/Os Power;
Conference_Titel :
Green Computing, Communication and Conservation of Energy (ICGCE), 2013 International Conference on
Conference_Location :
Chennai
DOI :
10.1109/ICGCE.2013.6823418
