Implementation of adder structure with fast carry network for high speed processor

High performance digital adder with reduced area and low power consumption is an important design constraint for advanced processors. The speed of operation of such an adder is limited by carry propagation from input to output. Our work is based on designing an optimized adder for advanced processors. This paper discusses about the implementation of Carry Select Adder combining with the possibilities of Kogge Stone Adder. Kogge Stone parallel approach will give option to generate fast carry for intermediate stages. The adder is implemented on Xilinx Virtex 5 FPGA devices and is compared with RCA adder and Kogge Stone adder. Result shows the adder gives better performance in terms of speed and area implementation.