Design and implementation of low power floating point arithmetic unit

Author

Kukati, Shilpa ; Sujana, D.V. ; Udaykumar, Shruthi ; Jayakrishnan, P. ; Dhanabal, R.

Author_Institution

Sch. of Electron. Eng., VIT Univ., Vellore, India

fYear

2013

fDate

12-14 Dec. 2013

Firstpage

205

Lastpage

208

Abstract

This paper proposes implementation of IEEE floating point (FP) multiplication, addition and subtraction. Arithmetic on IEEE FP numbers imposes more challenges compared to fixed-point arithmetic. These particularly include the simultaneous computation of normalization and rounding. We show the efficient way of solving these challenges for the implementation of floating point (FP) addition, subtraction and multiplication. The proposed designs aim at reducing power dissipation. Here multi threshold voltage technique is used for reducing power dissipation. The proposed implementations are according to the IEEE 754 FP standard.

Keywords

floating point arithmetic; power aware computing; IEEE 754 FP standard; IEEE floating point multiplication; fixed-point arithmetic; floating point addition; floating point subtraction; low power floating point arithmetic unit; multithreshold voltage technique; power dissipation reduction; Adders; Floating-point arithmetic; Libraries; Logic gates; Optimization; Standards; Threshold voltage; Floating Point Representation; IEEE 754 standard; Multi Threshold Voltage (MVT) Technique;

fLanguage

English

Publisher

ieee

Conference_Titel

Green Computing, Communication and Conservation of Energy (ICGCE), 2013 International Conference on

Conference_Location

Chennai

Type

conf

DOI

10.1109/ICGCE.2013.6823429

Filename

6823429