Survey and Analysis of Delay-Locked Loops Used in DRAM Interfaces

In this paper, delay-locked loops (DLLs) used in dynamic random access memory (DRAM) are analyzed. DLLs can be categorized into digital- or analog-based topologies. This analysis starts with an explanation of technology trends regarding DLL for DRAM in the early 1990s and describes important DLL specifications and design approaches necessary for DLL use in DRAM: lock time, lock range, lock cycles, tDQSCK (DQS rising edge output access time from the rising edge of CK), and wake-up time from power down modes. DLLs have been widely used since 2000 to satisfy high operating speed requirements inherent in DRAMs. Finally, referring to studies published from 2000 to 2011, trends regarding power consumption, jitter, relationship between power and jitter, lock range, lock cycles, and wake-up time from power down are analyzed.