Title :
Germanium p-Channel FinFET Fabricated by Aspect Ratio Trapping
Author :
van Dal, M.J.H. ; Vellianitis, G. ; Duriez, Blandine ; Doornbos, G. ; Chih-Hua Hsieh ; Bi-Hui Lee ; Kai-Min Yin ; Passlack, Matthias ; Diaz, Carlos H.
Author_Institution :
Logic Adv. Dev. Div., Taiwan Semicond. Manuf. Co., Leuven, Belgium
Abstract :
We report scaled Ge p-channel FinFETs fabricated on a 300-mm Si wafer using the aspect-ratio-trapping technique. For long-channel devices, a combination of a trap-assisted tunneling and a band-to-band tunneling leakage mechanism is responsible for an elevated bulk current limiting the OFF-state drain current. However, the latter can be mitigated by device design. We report low long-channel subthreshold swing of 76 mV/decade at VDS=-0.5 V, good short-channel effect control, and high transconductance (gm=1.2 mS/μm at VDS=-1 V and 1.05 mS/μm at VDS=-0.5 V for LG=70 nm). The Ge FinFET presented in this paper exhibits the highest gm/SSsat at VDD=1 V reported for nonplanar unstrained Ge p-FETs to date.
Keywords :
MOSFET; electron traps; elemental semiconductors; epitaxial growth; germanium; hole traps; tunnelling; Ge; Si; aspect ratio trapping; band-to-band tunneling leakage mechanism; elevated bulk current limit; nonplanar unstrained p-FET; off state drain current; p-channel FinFET; short channel effect control; size 300 nm; trap assisted tunneling; voltage -0.5 V; voltage -1 V; Current measurement; Epitaxial growth; FinFETs; Logic gates; Silicon; Subspace constraints; Temperature measurement; Aspect ratio trapping (ART); FinFET; band-to-band tunneling (BTBT); epitaxy; germanium; scaling; trap-assisted tunneling (TAT);
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2013.2295883