The first stage design of a SHA-less 12-bit 200-Ms/s pipeline ADC in 130-nm CMOS

Author

Yongsheng Yin ; Xiangyang Jiang ; Honghui Deng

Author_Institution

Inst. of VLSI Design, Hefei Univ. of Technol., Hefei, China

fYear

2013

fDate

25-27 Oct. 2013

Firstpage

1

Lastpage

5

Abstract

A first stage of a SHA-less 12-bit 200 MSps pipeline analog-to-digital converter (ADC) is designed in this paper. A high speed and high precision comparator is designed in order to reduce the transmission delay of the comparator. RC network of the multiplying digital-to-analog converter (MDAC) and Sub-ADC should be strict matched in order to reduce the sampling errors between the two path. The prototype circuit, implemented in SMIC 130nm 1P5M CMOS process under 1.2V power supply with a 94MHz input signal and 200MHz sampling clock, demonstrates a SNDR of 82.7dB, a SNR of 72.6dB, and a ENOB of 11.83 bit.

Keywords

CMOS digital integrated circuits; amplifiers; analogue-digital conversion; comparators (circuits); sample and hold circuits; ENOB; MDAC; RC network; SHA-less; SMIC 1P5M CMOS process; analog-to-digital converter; frequency 200 MHz; frequency 94 MHz; high precision comparator; high speed comparator; multiplying digital-to-analog converter; pipeline ADC; sample and hold amplifier; sampling errors; size 130 nm; sub-ADC; transmission delay; voltage 1.2 V; word length 12 bit; ADC; Comparator; Pipeline; SHA-less;

fLanguage

English

Publisher

ieee

Conference_Titel

Anti-Counterfeiting, Security and Identification (ASID), 2013 IEEE International Conference on

Conference_Location

Shanghai

Type

conf

DOI

10.1109/ICASID.2013.6825291

Filename

6825291