A double sampling S/H circuit for dual-channel pipelined ADC based on op-sharing

A double sampling and holding (S/H) circuit which can be used in a 12 bit 200Ms/s dual-channel pipelined analog-to-digital converter (ADC) based on op-amp sharing (op-sharing) is presented in this paper. Additional reset switches connecting the feedback capacitors are used to remove the memory effect. Through the design of a two-phase non-overlapping clock generation circuit and modifying the timing of actual work, the impact of sampling time interval mismatch between two channels is eliminated. The simulation by Cadence based on 0.13um CMOS process under 1.2-V supply voltage, shows that the S/H achieves a SNDR of 81.55 dB, a SFDR of 86.64dB under an input signal bandwidth of 99.6MHz and a 0.6-Vpp-diff input voltage range.