Dynamic latched comparator design for super-high speed analog-to-digital converter

As a building block of analog-to-digital converter (ADC), comparator plays an important role, especially the case latched comparator for super-high speed ADC. The speed and performance of latched comparator mostly decide the performance of the whole ADC. In this paper, a multi-stage purely dynamic high speed latched comparator for folding and interpolating ADC is designed with Bi-CMOS 0.18um process technology. The folding and interpolating ADC is employed in a four channel time interleaved ADC as a sub-ADC. The whole ADC can reach a sampling rate of 5GSPS at interleaved mode. As a result of measurement, the whole ADC can get a SNR of 45dB with the input frequency of 495MHz at the sample rate of 5GHz.