Modeling and implementation of CPPLL

Author

Honghui Deng ; Chao Li ; Shangming Huang

Author_Institution

Inst. of VLSI Design, Hefei Univ. of Technol., Hefei, China

fYear

2013

fDate

25-27 Oct. 2013

Firstpage

1

Lastpage

5

Abstract

Based on the model of SMIC 0.13 mixed-signal process and its supply voltage is 3.3 V, a Charge Pump Phase-Locked Loop is designed in this paper. The Verilog-A language is applied to build the behavioral modeling for the Charge Pump Phase-Locked Loop, in the bias circuit of Charge Pump a voltage regulation NMOS is added to reduce the charging and discharging current mismatch to less than 0.073%, and the design parameters of the Loop Low-Pass Filter is given in this paper. The Cadence simulation results show that the frequency of the input of the Charge Pump Phase-Locked Loop is 3~160MHz, and the output frequency is 3~400MHz; the maximum division number is 32 and the lock time is less than 22us.

Keywords

charge pump circuits; hardware description languages; low-pass filters; mixed analogue-digital integrated circuits; phase locked loops; Cadence simulation; NMOS; SMIC; Verilog-A language; bias circuit; charge pump phase-locked loop; frequency 3 MHz to 400 MHz; low-pass filter; mixed-signal process; voltage 3.3 V; voltage regulation; Decision support systems; Hafnium; CPPLL; Charge Pump; The Loop Filter; Verilog-A modeling; Voltage-Controlled Oscillator;

fLanguage

English

Publisher

ieee

Conference_Titel

Anti-Counterfeiting, Security and Identification (ASID), 2013 IEEE International Conference on

Conference_Location

Shanghai

Type

conf

DOI

10.1109/ICASID.2013.6825303

Filename

6825303