Range selection of critical area optimization

With the fast growth of the microelectronic technology, the smaller and smaller feature size of IC (Integrated Circuit) and the increasing circuit complexity, the optimization of layout based on the distribution of defect is becoming more and more important. Firstly, associating critical area with edge network, a concept of shortest path of redundancy material defect is presented and realized. Secondly, from this, the maximum and minimum yields are derived respectively. Finally, a range of critical area optimization is capable of being ascertained which is a key parameter of layout improvement. Therefore, experiments result shows that the yield has a certain degree of optimization space by the calculation of the shortest path and current yield.