Analysis of timing resolution of a digital silicon photomultiplier

This paper presents the analysis of timing resolution for a digital silicon photomultiplier (D-SiPM) using a SPICE simulator. A D-SiPM has more than a hundred of pico seconds timing resolution for single-photon detection due to detector jitter, circuit noise and routing skew. Especially, circuit noise and skew depend on the SiPM design strongly. To investigate how single-photon timing resolution is related to architectural choices and design parameters, we have simulated the timing resolution by sweeping the design parameters: the transistor size and the transistor channel length, wire resistance and capacitance. We considered D-SiPMs of different sizes and with a variety of signal distribution architectures.