Time interleaved ADCs for high speed high resolution data acquisition system

Time Interleaving is one of the most effective techniques to increase the sampling rate of ADC and it is growing into a significant trend in performance enhancement for high speed ADC systems. With the requirements of High Purity Germanium (HPGe) Detectors, we need a high speed and high resolution ADC systems. In this paper, we introduce the architecture of four 500MHz 12bit ADCs interleaved to one 2000MHz 12bit ADC with high speed and high resolution. The analog front end and the 4 phase clock distribution networks are also introduced. Mismatch of analog front end between channels will lead to degraded performance if the allowable mismatch range of algorithm is exceeded, the analog front end and clock circuit´s PCB layout is also important for the performance of time interleaved ADCs, careful PCB layout, tightly matched front end circuit, tightly matched clock distribution circuit, common reference voltages and the detail of the practice will be also introduced in this paper. Furthermore, we introduce digital signal processing techniques to compensate the performance loss caused by offset error, time skew and gain error. At the end, the performance is measured by the signal to noise ratio.