FADC electronics design for HPGe detector

High Purity Germanium Detectors need two different type of Flash Analog to Digital Convertors to read out, one is the 8 channels 100MHz 14bits FADC for slow time shaping and another is the 1 channel 800MHz 12bits FADC for fast time shaping. In the CDEX experiment in CJPL China, we build a 10 Kg HPGe detector array for dark matter detect, a FADC electronics is needed for the HPGe detectors. In this paper, we introduce the architecture of the electronics of FADC for HPGE, the detail of analog to digital convertor circuits and PCB design, the detail of 800MHz 12bits FADC, and the read out of FADC, 1000Mbps Ethernet interface and VHDL which running in the FPGA will be also introduced in this paper. Furthermore, we introduce the system´s bench mark with more than 900Mbps Ethernet throughput and the ENOB of two type of FADC, trigger rate will also be introduced.