Discriminators in 65 nm CMOS process for high granularity, high time resolution pixel detectors

This work is meant to explore the limitations in the design of threshold discriminators employed as the final stage of the analog chain processing the signals from particle tracking pixellated detectors. The 65 nm CMOS technology, which is currently under scrutiny of the electronic designers in the high energy physics community, is the natural choice for this study. In the design of the discriminators, power dissipation, area, delay, delay dispersion and threshold dispersion (input offset), while calling for fairly different, sometimes opposite design choices, have to be concurrently optimized, in compliance with the specifications set by the application. For the purpose of investigating the boundaries set by the technology, a couple of different simple architectures have been studied and optimized under different parameter configurations. The paper will provide a set of rules for the constrained design of threshold discriminators in multichannel front-end chips for pixel detectors.