A new predistortion architecture with sampling clock jitter mitigation for wideband systems

The sampling clock accuracy of the digital predistortion (DPD) feedback path is limited by nonideal electronic components, which introduces random clock jitter and thus degrades the linearization performance. In this paper, we propose a new DPD architecture capable of estimating and mitigating the sampling clock jitter. The theoretical analysis reveals that the sampling clock jitter has a adverse effect on the signal-to-noise ratio (SNR) of the samples received and hence degrades the DPD performance. By applying the proposed reference injection method, the clock jitter can be estimated and mitigated, effectively. Simulation results demonstrate that the proposed DPD architecture can improve the normalized mean square error (NMSE) and the adjacent channel leakage ratio (ACLR) performances, compared with conventional DPD architecture when feedback sampling clock jitter is considered.