DocumentCode :
68816
Title :
Novel Single-Slope ADC Design for Full Well Capacity Expansion of CMOS Image Sensor
Author :
Shang-Fu Yeh ; Chih-Cheng Hsieh
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Volume :
13
Issue :
3
fYear :
2013
fDate :
Mar-13
Firstpage :
1012
Lastpage :
1017
Abstract :
This paper proposes a novel single-slope (SS) ADC design and operation for full well capacity (FWC) expansion of CMOS image sensor to increase the dynamic range for small pixel. With the proposed technique, charges stored in the photodiode and floating diffusion of 4T active pixel sensor are all read out and accumulated by the proposed SS ADC to improve the FWC. Only one A/D conversion is required for each pixel, which decreases chip power consumption compared with the general double A/D conversion operation. A 160×140 CMOS image sensor chip with the proposed SS ADC is fabricated using 0.18-μm CMOS image sensors technology. This chip achieves a sensitivity of 5.33 V/lx·s and a FWC expansion ratio of 2.18 at 38.5 fps. The measured FWC is 47.45 ke- with 118% boost. The ADC resolution is 8 bits and the resulting differential nonlinearity/integral nonlinearity of proposed column-parallel SS ADC is (+0.16,-0.24)/(+0.28,-0.52) least significant bit. The column-fixed pattern noise is 0.16%.
Keywords :
CMOS image sensors; analogue-digital conversion; 4T active pixel sensor; CMOS image sensor; column-fixed pattern noise; floating diffusion; full well capacity expansion; photodiode; single-slope ADC design; Capacitors; Lighting; Noise; Photodiodes; Sensitivity; Threshold voltage; Turning; CMOS image sensor; full well capacity; single slope ADC; small dimension pixel;
fLanguage :
English
Journal_Title :
Sensors Journal, IEEE
Publisher :
ieee
ISSN :
1530-437X
Type :
jour
DOI :
10.1109/JSEN.2012.2227706
Filename :
6353877
Link To Document :
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