An Efficient Topology Reconfiguration Algorithm for NoC Based Multiprocessor Arrays

To realize the reliability of a high-performance multiprocessor system with a reconfigurable interconnect, there is a need to compute a interconnect topology that will allow for a high-throughput load distribution on top of the physical processor array. In this paper, we investigate the problem of topology reconfiguration for Network on Chip (NoC) based multiprocessor arrays with faulty processing elements (PEs). We propose two types of shift operations, i.e. row bi-shift operation and column shift operation, for redistributing fault-free PEs of a processor array in reconfiguration. We solve the topology reconfiguration problem by developing two efficient algorithms. The first algorithm, denoted as CRS, is able to generate a logical topology of desirable communication performance by alternately performing the two shift operations. The second algorithm revises the initial topology produced by CRS to further improve the communication performance, using tabu search techniques. Experimental results validate the efficiency of the proposed algorithm in comparison to previous approaches. For 16*16 physical arrays with 30% faulty PEs, the proposed approaches improve existing algorithms up to 39% in terms of message latency and congestion.