An Energy-Efficient Scheme for STT-RAM L1 Cache

Spin-Transfer Torque RAM (STT-RAM) is a promising cache candidate studied frequently in recent years. Compared to the traditional SRAM, The STT-RAM is more promising for future on-chip caches due to STT-RAM´s long endurance, low leakage, high density and high access speed. Nevertheless, the major challenges of using STT-RAM as L1 cache are its write energy and write latency. It is feasible to use STT-RAM as L1 cache by reducing data retention time. We find that most data in L1 cache has a life time shorter than STT-RAM data retention time. A refresh scheme that will degrades system performance, and bring more energy consumption is needed to assure data correctness. In this paper, we proposed a counter-controlled scheme to avoid STT-RAM L1 cache data block refreshing. We propose a dead data processing strategy that deals with data block when it exceeds its retention time. Our simulation results show that STT-RAM L1 cache coupled with our counter-controlled scheme can save up to 60% energy consumption, 44% energy consumption on average compared to SRAM L1 cache, achieve slightly performance improvement on average compared to baseline.