Low Energy Mapping Techniques under Reliability and Bandwidth Constraints

The energy consumed by the links of a Network-on-Chip (NoC) accounts for a significant fraction of the overall energy budget in a multi/many-core system. Reducing voltage of the links allows to save energy but at the cost of an increase of the bit error rate (BER). Since different communications might have different reliability (i.e., BER) requirements, in this paper we present a new mapping technique aimed at optimising the static allocation of the tasks into the nodes of the NoC and determining the optimal link voltage swing for minimising the energy consumption under bandwidth and reliability constraints.