DocumentCode :
68986
Title :
Simulation to Study the Effect of Oxide Thickness and High- 
Dielectric on Drain-Induced Barrier Lowering in N-type MOSFET
Author :
Das, S. ; Kundu, Sandipan
Author_Institution :
Dept. of Comput. Sci. & Eng., West Bengal Univ. of Technol., Kolkata, India
Volume :
12
Issue :
6
fYear :
2013
fDate :
Nov. 2013
Firstpage :
945
Lastpage :
947
Abstract :
The effect of variation of oxide thickness on the drain-induced barrier lowering, simulation parameter of a conventional MOSFET has been studied, first theoretically by proposing a new numerical method and then verifying by simulating with Sentaurus TCAD Toolkit. Since SiO2 has its limitations at very low oxide thicknesses, improvement in the performance of the MOS by using high- K dielectric material for gate-channel isolation has also been studied.
Keywords :
MOSFET; electronic engineering computing; high-k dielectric thin films; technology CAD (electronics); N-type MOSFET; Sentaurus TCAD Toolkit; SiO2; drain-induced barrier lowering; gate-channel isolation; high-K dielectric material; numerical method; oxide thickness effect; silicon dioxide; simulation parameter; Dielectrics; High K dielectric materials; Logic gates; MOSFET; MOSFET circuits; Permittivity; Drain-induced barrier lowering (DIBL); high-$k$
fLanguage :
English
Journal_Title :
Nanotechnology, IEEE Transactions on
Publisher :
ieee
ISSN :
1536-125X
Type :
jour
DOI :
10.1109/TNANO.2013.2276441
Filename :
6574275
Link To Document :
